1. Field of the Invention
This invention relates generally to a method and apparatus for processing a microprogram for the execution of a machine language instruction in a computer controlled by a microprogram, and particularly to a central processing unit having loosely coupled pipeline stages.
2. Prior Art
One example of conventional pipeline processors is described in "Branch Prediction Strategies and Branch Target Buffer Design" by Jonny K. F. Lee and Alan Jay Smith, on pages 6-22 in COMPUTER; IEEE 1984 (17). A conventional pipeline processor comprises an instruction decorder, an operand address computation unit, an operand pre-fetch unit, and an arithmetic unit, and each unit processes an instruction by a cascade system. In the instruction decoder, an instruction code is decoded and control information for an instruction execution is sent to a following device. In the operand pre-fetch unit, the reading of data is performed in accordance with a computed address sent from the operand address computation unit. Here, when the fetch of an operand is required, such read data and the control information for the instruction execution are sent to the arithmetic unit. When the fetch of an operand is not required, control information for the instruction execution is sent to the arithmetic unit. It is to be noted that the control information is passed through pipeline stages relating to the fetch of the operand even when the fetch of the operand address is not required. As a result, there is a drawback that bus band width is limitted by unnecessary passing of the control information.